In the field of synchronous digital integrated circuit (IC) devices, scan chains are a technique used in design for testing that provide a simple way to set and observe flip-flops within an IC device. Scan chains are implemented by way of scan flip-flops. Scan flip-flops are flip-flop circuits that have been adapted to include additional scan-in and scan-enable signals that enable multiple scan flip-flops to be configured into scan chains.
A link layer communications protocol is used in internal high-speed connections within computer systems and embedded systems. High speed link layer communications protocol interfaces have a working frequency in the Gigahertz range, for example 2.5 GHz or 5 GHz. A problem with developing interfaces to work at such high frequency ranges is that existing scan flip-flop structures are not capable of achieving the required operating speeds.